公开(公告)号：US20130222029A1

公开(公告)日：2013-08-29

申请号：US13756283

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Benjamin J. Bowers ,  Joshua L. Puckett

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G06F9/3869 ,  H03K5/135

Abstract: A hold pulse latch is located in a data path between an output of a launch pulse latch and an input of a capture pulse latch. The hold pulse latch is configured to latch, and hold for the input of the capture patch, the output of the launch pulse latch in response to a hold pulse on its enable input. Optionally, at higher voltages, and frequency is high the launch pulse latch is changed to a transparent buffer mode. Optionally, the hold pulse latch is placed midway through the logic path between the launch pulse latch and the capture pulse latch.

Abstract translation: 保持脉冲锁存器位于发射脉冲锁存器的输出和捕获脉冲锁存器的输入之间的数据路径中。 保持脉冲锁存器被配置为响应于其使能输入上的保持脉冲来锁存并保持捕获补丁的输入，启动脉冲锁存器的输出。 可选地，在较高电压下，并且频率高，启动脉冲锁存器被改变为透明缓冲器模式。 可选地，保持脉冲锁存器位于启动脉冲锁存器和捕获脉冲锁存器之间的逻辑路径的中途。

公开(公告)号：US09093125B2

公开(公告)日：2015-07-28

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM Incorporated

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passgate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定显示WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）通孔 晶体管被打开。

公开(公告)号：US20130188434A1

公开(公告)日：2013-07-25

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM INCORPORATED

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passe ate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定表明WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）passe 打开晶体管。