公开(公告)号：US10115480B1

公开(公告)日：2018-10-30

申请号：US15640855

申请日：2017-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： Lakshmi Neeharika Gamini ,  Sanku Mukherjee

IPC: G11C29/50 ,  G11C29/38 ,  G11C29/12 ,  G11C11/4076 ,  G11C11/409

Abstract: In calibrating the phase skew between an SDRAM data strobe (“DQS”) signal and data (“DQ”) signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests may emulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.