公开(公告)号：US11929766B2

公开(公告)日：2024-03-12

申请号：US17659468

申请日：2022-04-15

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Brian Clarke Banister ,  Christos Komninakis ,  Minkui Liu

IPC: H04B1/26 ,  H04B1/00 ,  H04B1/403 ,  H04B1/58

CPC classification number: H04B1/0007 ,  H04B1/0053 ,  H04B1/403 ,  H04B1/588

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

公开(公告)号：US20140179303A1

公开(公告)日：2014-06-26

申请号：US13724995

申请日：2012-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Insung Kang ,  Aamod Dinkar Khandekar ,  Minkui Liu ,  Ming Kang ,  Shaiu-He Tsai ,  Qingxin Chen

IPC: H04W24/08

CPC classification number: H04W24/08 ,  H04W24/10 ,  H04W88/02

Abstract: A method of wireless communication enables an inter-radio access technology (IRAT) neighbor cell measurement when a serving RAT signal strength is continuously below a first threshold value for a first length of time. The method also disables the IRAT neighbor cell measurement when the serving RAT signal strength is continuously above a second threshold value for a second length of time.

Abstract translation: 当第一时间长度的服务RAT信号强度连续低于第一阈值时，无线通信的方法能够实现无线电接入技术（IRAT）相邻小区测量。 当服务RAT信号强度持续高于第二阈值持续第二时间长度时，该方法还禁用IRAT相邻小区测量。

公开(公告)号：US20140362744A1

公开(公告)日：2014-12-11

申请号：US14061536

申请日：2013-10-23

Applicant: Qualcomm Incorporated

Inventor： Hongbo YAN ,  Insung Kang ,  Daniel Fred Filipovic ,  Michael Mingxi Fan ,  Ning He ,  Minkui Liu

IPC: H04B7/26 ,  H04W52/34

CPC classification number: H04B7/26 ,  H04B7/0404 ,  H04B7/0608 ,  H04W52/34 ,  H04W52/42

Abstract: TDD devices may transmit using multiple antennas. First and second antennas having first and second receive conditions may receive a communication. In an aspect, first and second transmit conditions for the first and second antennas may be determined based on the first and second receive conditions. In an aspect, the first and second transmit conditions may be compared to select the first or second antenna for transmissions. In an aspect, the first and second receive conditions may be compared to select the first or second antenna for transmissions. In an aspect, first and second transmission conditioning values, which may determine transmission powers, may be determined based on the first and second receive conditions. A first transmission chain, associated with an active RAT or carrier, and a second transmission chain, associated with an inactive RAT or carrier, may be activated to send transmissions from the first and second antennas.

Abstract translation: TDD设备可以使用多个天线发射。 具有第一和第二接收条件的第一和第二天线可以接收通信。 在一方面，可以基于第一和第二接收条件来确定用于第一和第二天线的第一和第二发射条件。 在一个方面，可以比较第一和第二发射条件以选择用于传输的第一或第二天线。 在一个方面，可以比较第一和第二接收条件以选择用于传输的第一或第二天线。 在一方面，可以基于第一和第二接收条件来确定可以确定发射功率的第一和第二传输调节值。 可以激活与非活动RAT或载波相关联的与主动RAT或载波相关联的第一传输链和第二传输链，以从第一和第二天线发送传输。

公开(公告)号：US11968288B2

公开(公告)日：2024-04-23

申请号：US17659469

申请日：2022-04-15

Applicant: QUALCOMM Incorporated

Inventor： Lennart Karl-Axel Mathe ,  Brian Clarke Banister ,  Christos Komninakis ,  Minkui Liu

IPC: H04L7/00 ,  H03M1/12 ,  H04W56/00

CPC classification number: H04L7/0079 ,  H03M1/1245 ,  H04W56/005

Abstract: An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.