公开(公告)号：US20240037042A1

公开(公告)日：2024-02-01

申请号：US18340291

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Ajay Kumar Rathee ,  Conrado Blasco

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1021

Abstract: Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

公开(公告)号：US20240385841A1

公开(公告)日：2024-11-21

申请号：US18594899

申请日：2024-03-04

Applicant: QUALCOMM Incorporated

Inventor： Conrado Blasco ,  Ajay Kumar Rathee ,  Huzefa Sanjeliwala

IPC: G06F9/38

Abstract: Fetching beyond predicted-taken branch instructions in fetch bundles of processor-based devices is disclosed. In exemplary aspects, a processor-based device comprises an instruction processing circuit configured to process an instruction stream in an instruction pipeline. The instruction processing circuit comprises an instruction fetch circuit configured to generate a fetch bundle comprising a plurality of fetched instructions from the instruction stream, wherein a last fetched instruction of the plurality of fetched instructions is a predicted-taken branch instruction. The instruction processing circuit is further configured to identify the plurality of fetched instructions as a loop iteration. The instruction processing circuit is also configured to determine that at least one loop iteration copy fits within the fetch bundle. The instruction processing circuit is additionally configured to, responsive to determining that the at least one loop iteration copy fits within the fetch bundle, store the at least one loop iteration copy within the fetch bundle.

公开(公告)号：US20240264949A1

公开(公告)日：2024-08-08

申请号：US18626488

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Ajay Kumar Rathee ,  Conrado Blasco

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1021

Abstract: Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

公开(公告)号：US20240036864A1

公开(公告)日：2024-02-01

申请号：US17816513

申请日：2022-08-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket Bhivasen Bhor ,  Huzefa Sanjeliwala ,  Ajay Kumar Rathee

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3814 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/3861

Abstract: An apparatus includes a circular buffer which includes a fixed number of entries and allows data overflow to occur while maintaining the most recently stored entries in order. The circular buffer could be used as a return address stack used to push and pop return addresses for subroutine calls in a processor. Additional circuitry dynamically links entries to maintain a last-in first-out stack. A system return pointer tracks the next entry to be returned when an entry is to be read. When data is pushed to an entry in the circular buffer, that entry stores a pointer to the entry for the previous system return pointer. By tracking the previous system return pointer in the pushed entry, the dynamically linked entries may skip intervening entries that have been previously popped and, thus, track the order of most recently written non-popped entries without having to separately maintain free and used lists.