公开(公告)号：US20230057276A1

公开(公告)日：2023-02-23

申请号：US17405860

申请日：2021-08-18

Applicant: QUALCOMM Incorporated

Inventor： Luca MATTII ,  Sidharth RASTOGI ,  Ranganayakulu KONDURI ,  Gerard Patrick BALDWIN ,  Angelo PINTO

IPC: H01L23/528

Abstract: Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.

公开(公告)号：US20230022681A1

公开(公告)日：2023-01-26

申请号：US17383208

申请日：2021-07-22

Applicant: QUALCOMM Incorporated

Inventor： Sidharth RASTOGI ,  Luca MATTII ,  Gerard Patrick BALDWIN ,  Angelo PINTO ,  Satadru SARKAR ,  David KIDD ,  Ardavan MOASSESSI ,  Paul PENZES

IPC: H01L27/02 ,  H01L27/118

Abstract: In a first aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having a pitch that is uniform among the plurality of wrapped channels. In a second aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having an asymmetric distribution. For example, a first distance between a first pair of adjacent wrapped channels is different than a second distance between a second pair of adjacent wrapped channels.