公开(公告)号：US20230022681A1

公开(公告)日：2023-01-26

申请号：US17383208

申请日：2021-07-22

Applicant: QUALCOMM Incorporated

Inventor： Sidharth RASTOGI ,  Luca MATTII ,  Gerard Patrick BALDWIN ,  Angelo PINTO ,  Satadru SARKAR ,  David KIDD ,  Ardavan MOASSESSI ,  Paul PENZES

IPC: H01L27/02 ,  H01L27/118

Abstract: In a first aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having a pitch that is uniform among the plurality of wrapped channels. In a second aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having an asymmetric distribution. For example, a first distance between a first pair of adjacent wrapped channels is different than a second distance between a second pair of adjacent wrapped channels.

公开(公告)号：US20230099295A1

公开(公告)日：2023-03-30

申请号：US17485140

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Arjang SHAHRIARI ,  Ajay VADAKKEPATT ,  Ajit Kumar VALLABHANENI ,  Melika ROSHANDELL ,  Mahdi NABIL ,  Mehdi SAEIDI ,  Paul PENZES

IPC: G02B26/00 ,  G09G3/34 ,  H01L23/473

Abstract: A device that includes a first integrated device, a second integrated device configured to be electrically coupled to the first integrated device and an electrowetting device configured to be electrically coupled to the second integrated device. The electrowetting device is configured to redistribute heat across a back surface of the device by looping a liquid in the electrowetting device, along the back surface of the device.

公开(公告)号：US20190058477A1

公开(公告)日：2019-02-21

申请号：US15680643

申请日：2017-08-18

Applicant: QUALCOMM Incorporated

Inventor： Albert KUMAR ,  Ramaprasath VILANGUDIPITCHAI ,  Vasisht VADI ,  Paul PENZES

IPC: H03K19/0185 ,  H01L27/06 ,  H01L29/06

Abstract: A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit.