CACHE MEMORY ARCHITECTURE AUGMENTATION FOR 3-DIMENSIONAL (3D) DATA

    公开(公告)号:US20250117876A1

    公开(公告)日:2025-04-10

    申请号:US18481909

    申请日:2023-10-05

    Abstract: Aspects of the disclosure are directed to reordering a plurality of input block voxel indices in a cache memory. In accordance with one aspect, an apparatus including a create block configured to receive the plurality of input block voxel indices and configured to generate a reordered list based on the plurality of input block voxel indices; and an integrate block coupled to the create block, the integrate block configured to use the reordered list to deliver integrate depth data for generating a plurality of output block voxel indices. In accordance with one aspect, a method including reordering the plurality of input block voxel indices into a plurality of output block voxel indices using a separated set of input block voxel indices; and accessing the plurality of output block voxel indices to provide an augmented cache memory access.

Patent Agency Ranking