公开(公告)号：US20210157380A1

公开(公告)日：2021-05-27

申请号：US16696073

申请日：2019-11-26

Applicant: QUALCOMM Incorporated

Inventor： Anubha MOTWANI ,  Kaustav ROYCHOWDHURY ,  Siddesh HALAVARTHI MATH REVANA

IPC: G06F1/324 ,  G06F1/08 ,  G06F13/10

Abstract: In some aspects, the present disclosure provides a method for scaling a core processor clock to reduce power consumption. The method includes retrieving, by an advanced peripheral bus (APB) driver, a first one or more values from one or more registers of a core processor, the first one or more values corresponding to a set of instructions of the core processor. The method may also include determining, by an IPC calculator, a first expected instruction per cycle (IPC) for executing the set of instructions based on the first one or more values. The method may also include comparing, by the IPC calculator, a threshold IPC to the first expected IPC to determine whether an equality condition is met, wherein the threshold IPC is stored in a first register of the IPC calculator.