公开(公告)号：US20200264788A1

公开(公告)日：2020-08-20

申请号：US16277668

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Kaustav ROYCHOWDHURY ,  Siddesh HALAVARTHI MATH REVANA

IPC: G06F3/06 ,  G06F12/084

Abstract: Systems and methods for memory power management may receive a wake up event in retention mode that may be used to control three memory sequencers that wake up respective groups of memory sequencers.

公开(公告)号：US20210157380A1

公开(公告)日：2021-05-27

申请号：US16696073

申请日：2019-11-26

Applicant: QUALCOMM Incorporated

Inventor： Anubha MOTWANI ,  Kaustav ROYCHOWDHURY ,  Siddesh HALAVARTHI MATH REVANA

IPC: G06F1/324 ,  G06F1/08 ,  G06F13/10

Abstract: In some aspects, the present disclosure provides a method for scaling a core processor clock to reduce power consumption. The method includes retrieving, by an advanced peripheral bus (APB) driver, a first one or more values from one or more registers of a core processor, the first one or more values corresponding to a set of instructions of the core processor. The method may also include determining, by an IPC calculator, a first expected instruction per cycle (IPC) for executing the set of instructions based on the first one or more values. The method may also include comparing, by the IPC calculator, a threshold IPC to the first expected IPC to determine whether an equality condition is met, wherein the threshold IPC is stored in a first register of the IPC calculator.

公开(公告)号：US20190332166A1

公开(公告)日：2019-10-31

申请号：US15964069

申请日：2018-04-27

Applicant: QUALCOMM Incorporated

Inventor： Siddesh HALAVARTHI MATH REVANA ,  Kaustav ROYCHOWDHURY

IPC: G06F1/32 ,  G06F12/1045 ,  G06F1/28

Abstract: A system is disclosed. The system comprises a set-associative memory cache comprising a plurality of ways, a plurality of way power controllers (WPCs), each WPC being respectively associated with a respective way of the plurality of ways, and a cache controller. The cache controller is configured to provide a way activation signal to each of the plurality of WPCs, wherein the way activation signal includes either a power relay signal or a power mask signal. Each of the plurality of WPCs is configured to receive a power management signal, relay the power management signal to the respective way in response to a determination that the way activation signal is a power relay signal, and mask the power management signal to the respective way in response to a determination that the way activation signal is a power mask signal.