公开(公告)号：US20180041614A1

公开(公告)日：2018-02-08

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

公开(公告)号：US09998573B2

公开(公告)日：2018-06-12

申请号：US15226429

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal ,  Ayala Miller ,  Shaul Yohai Yifrach

IPC: H04L12/28 ,  H04L29/06 ,  H04L12/741 ,  H04L12/749

CPC classification number: H04L69/22 ,  H04L45/741 ,  H04L45/745 ,  H04L69/04 ,  H04L69/08 ,  H04L69/18 ,  H04L69/321

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.