公开(公告)号：US11335683B2

公开(公告)日：2022-05-17

申请号：US16917451

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  ChihWei Kuo ,  Junjing Bao

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

公开(公告)号：US10854604B1

公开(公告)日：2020-12-01

申请号：US16578101

申请日：2019-09-20

Applicant: QUALCOMM Incorporated

Inventor： ChihWei Kuo ,  Haining Yang ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H03K19/0185 ,  H02M7/515

Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.