公开(公告)号：US20240379679A1

公开(公告)日：2024-11-14

申请号：US18314245

申请日：2023-05-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Jun Yuan

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

Abstract: A 3D dual complementary-circuit structure includes a first forksheet structure stacked on a first side of, in a first direction, a second forksheet structure to provide two complementary circuits in a space of a single forksheet structure. A dividing wall bisects at least one semiconductor slab in the first forksheet structure into a first slab portion with a first semiconductor type and a second slab portion with a second semiconductor type and also bisects at least one semiconductor slab in the second forksheet structure into a third slab portion with a third semiconductor type and a fourth slab portion with a fourth semiconductor type. One of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type may be a same semiconductor type as the first semiconductor type. Two complementary metal oxide semiconductor (CMOS) circuits may be formed in the area of a single forksheet structure.

公开(公告)号：US09601617B2

公开(公告)日：2017-03-21

申请号：US14604544

申请日：2015-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Xia Li ,  Bin Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

公开(公告)号：US11257917B2

公开(公告)日：2022-02-22

申请号：US16893993

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/06

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：US10247617B2

公开(公告)日：2019-04-02

申请号：US15246006

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  G01K7/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  G01K7/18 ,  H01L23/34 ,  H01L23/522 ,  H01L27/06

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US10090305B2

公开(公告)日：2018-10-02

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US20180076197A1

公开(公告)日：2018-03-15

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/785

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

公开(公告)号：US20180006035A1

公开(公告)日：2018-01-04

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/7846

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US20160172456A1

公开(公告)日：2016-06-16

申请号：US14567925

申请日：2014-12-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Bin Yang ,  Jun Yuan ,  Yu Lu

IPC: H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

Abstract translation: 半导体器件包括具有金属栅极，源极和漏极的晶体管。 半导体器件还包括位于晶体管的金属栅极上方的高电阻金属蚀刻停止层。 半导体器件还包括形成在高电阻金属蚀刻停止层上的金属层。 金属层位于晶体管的源极或晶体管的漏极中的至少一个的上方。

公开(公告)号：US09349656B2

公开(公告)日：2016-05-24

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/47 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US11145654B2

公开(公告)日：2021-10-12

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong Lim ,  Stanley Seungchul Song ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.