公开(公告)号：US20240079407A1

公开(公告)日：2024-03-07

申请号：US17939392

申请日：2022-09-07

Applicant: QUALCOMM Incorporated

Inventor： Thomas Hua-Min WILLIAMS ,  Conor ROCHE ,  Khaja Ahmad SHAIK ,  Hanil LEE ,  Roger Lee MILLS ,  Benjamin GRIFFITTS

IPC: H01L27/088 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L29/4238

Abstract: A chip includes a first active region, first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor, and second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor.

公开(公告)号：US20250040456A1

公开(公告)日：2025-01-30

申请号：US18715921

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Hua-Min WILLIAMS ,  Khaja Ahmad SHAIK ,  Conor ROCHE ,  Hanil LEE ,  Roger Lee MILLS ,  Keyurkumar Karsanbhai KANSAGRA ,  Smeeta HEGGOND ,  Giby SAMSON

IPC: H10N70/20 ,  H10N79/00

Abstract: In certain aspects, a die includes fins extending in a first direction, gates formed over the fins, wherein the gates extend in a second direction that is perpendicular to the first direction, and source/drain contact layers formed over the fins, wherein the source/drain contact layers extend in the second direction, and the gates and the source/drain contact layers are interleaved. The die also includes a first gate metal layer, a second gate metal layer, wherein the source/drain contact layers are between the first gate metal layer and the second gate metal layer in the second direction, first gate vias electrically coupling the first gate metal layer to the gates, and second gate vias electrically coupling the second gate metal layer to the gates.