公开(公告)号：US20170089974A1

公开(公告)日：2017-03-30

申请号：US15015547

申请日：2016-02-04

Applicant: QUALCOMM Incorporated

Inventor： Yu PU ,  Giby SAMSON ,  Kendrick Hoy Leong YUEN

IPC: G01R31/28

CPC classification number: G01R31/2851 ,  G01R31/2884 ,  G01R31/3004 ,  H01L22/14 ,  H01L22/34

Abstract: Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.

公开(公告)号：US20200341537A1

公开(公告)日：2020-10-29

申请号：US16395705

申请日：2019-04-26

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Seung Hyuk KANG ,  Eunjoo HWANG ,  Hai ZHU ,  Divjyot BHAN

IPC: G06F1/3296 ,  G06F1/28

Abstract: In certain aspects, a system comprises a power collapsible logic block, a plurality of retention flip-flops coupled to the power collapsible logic blocks, wherein the plurality of retention flip-flops includes a group of master-slave flip-flops and a group of balloon flip-flops, and a power controller configured to retain states of the group of balloon flip-flops and states of the group of master-slave flip-flops in a first sleep state and to retain the states of the group of balloon flip-flops but not states of the group of master-slave flip-flops in a deep sleep state.

公开(公告)号：US20180067539A1

公开(公告)日：2018-03-08

申请号：US15255176

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Parixit Laljibhai AGHERA ,  Adam Edward NEWHAM

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227

Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.

公开(公告)号：US20240322819A1

公开(公告)日：2024-09-26

申请号：US18188656

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Ramaprasath VILANGUDIPITCHAI ,  Pavan Kumar PATIBANDA ,  Joshua ONG ,  Chethan SWAMYNATHAN ,  Vajram GHANTASALA ,  Venugopal BOYNAPALLI ,  Madan KRISHNAPPA ,  Vineet OORAMKUMARATH ,  Mohamed Saud MUSLIYARAKATH

IPC: H03K17/687 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K17/6872 ,  H03K3/012 ,  H03K3/35625

Abstract: Aspects of the present disclosure provide cells including integrated switches and/or integrated clamps. In some aspects, a cell includes a circuit having an input and an output, and a switch coupled between a supply rail and the circuit, wherein the switch is configured to receive an enable signal, turn on when the enable signal has a first logic value, and turn off when the enable signal has a second logic value. The cell also includes a first clamp coupled to the output of the circuit, wherein the first clamp is configured to clamp the output of the circuit when the enable signal has the second logic value.

公开(公告)号：US20210110267A1

公开(公告)日：2021-04-15

申请号：US16599306

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Srivatsan CHELLAPPA ,  Ramaprasath VILANGUDIPITCHAI ,  Seung Hyuk KANG

IPC: G06N3/08 ,  G06N3/063 ,  G06F7/544

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

公开(公告)号：US20240428831A1

公开(公告)日：2024-12-26

申请号：US18340807

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chi-Jui CHEN ,  Xiao CHEN ,  Sonia GHOSH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Giby SAMSON

IPC: G11C5/14 ,  G11C11/417

Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.

公开(公告)号：US20170063092A1

公开(公告)日：2017-03-02

申请号：US14843983

申请日：2015-09-02

Applicant: QUALCOMM Incorporated

Inventor： Chunlei SHI ,  Yu PU ,  Kenneth David EASTON ,  Kendrick Hoy Leong YUEN ,  Giby SAMSON

IPC: H02J3/38

CPC classification number: H02J3/38 ,  G06F1/3287 ,  H02J2003/388 ,  H03K19/0016

Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Abstract translation: 用于为多个数字岛供电的可切换供电网络。 在一个实施例中，第一数字岛包括第一电源可折叠电路和第一保持电路，第二数字岛包括第二电源可折叠电路和第二保持电路。 在正常操作模式中，第一数字岛被提供第一电源电压，并且第二数字岛被提供有高于第一电源电压的第二电源电压。 在转换模式中，第二功率可折叠电路断电并且第二电源电压降低并提供给第二保持电路。 当第二电源电压低于第一电源电压时，第一电源可折叠电路断电。 现在仅向保持电路提供第二电源电压，并且在保持模式下进一步降低到最终的保持电压。

公开(公告)号：US20250040456A1

公开(公告)日：2025-01-30

申请号：US18715921

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Hua-Min WILLIAMS ,  Khaja Ahmad SHAIK ,  Conor ROCHE ,  Hanil LEE ,  Roger Lee MILLS ,  Keyurkumar Karsanbhai KANSAGRA ,  Smeeta HEGGOND ,  Giby SAMSON

IPC: H10N70/20 ,  H10N79/00

Abstract: In certain aspects, a die includes fins extending in a first direction, gates formed over the fins, wherein the gates extend in a second direction that is perpendicular to the first direction, and source/drain contact layers formed over the fins, wherein the source/drain contact layers extend in the second direction, and the gates and the source/drain contact layers are interleaved. The die also includes a first gate metal layer, a second gate metal layer, wherein the source/drain contact layers are between the first gate metal layer and the second gate metal layer in the second direction, first gate vias electrically coupling the first gate metal layer to the gates, and second gate vias electrically coupling the second gate metal layer to the gates.

公开(公告)号：US20230221789A1

公开(公告)日：2023-07-13

申请号：US18000319

申请日：2021-07-28

Applicant: QUALCOMM Incorporated

Inventor： Giby SAMSON ,  Smeeta HEGGOND ,  Jitu Khushalbhai MISTRY ,  Paras GUPTA ,  Keyurkumar Karsanbhai KANSAGRA ,  Kamesh MEDISETTI ,  Ramaprasath VILANGUDIPITCHAI ,  Arshath SHEEPARAMATTI

IPC: G06F1/3296 ,  G06F1/26 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/263 ,  G06F1/3275

Abstract: A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.