公开(公告)号：US20240221279A1

公开(公告)日：2024-07-04

申请号：US18609624

申请日：2024-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Dong Zhou

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a sliced low-resolution Z buffer (LRZ) that is communicatively coupled to each hardware slice of the plurality of hardware slices, and that comprises a plurality of LRZ regions. Each hardware slice is configured to store, in an LRZ region corresponding exclusively to the hardware slice among the plurality of LRZ regions, a pixel tile assigned to the hardware slice.