公开(公告)号：US20210399722A1

公开(公告)日：2021-12-23

申请号：US16906501

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Fadi HAMDAN ,  Keith Alan BOWMAN ,  Nadeem ELEYAN ,  Xiang LI

IPC: H03K5/133 ,  H03L7/081

Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

公开(公告)号：US20170345500A1

公开(公告)日：2017-11-30

申请号：US15369823

申请日：2016-12-05

Applicant: QUALCOMM Incorporated

Inventor： Kim Yaw TONG ,  Suresh Kumar VENKUMAHANTI ,  Fadi HAMDAN ,  Kun MA

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C7/1006 ,  G11C15/00

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.