公开(公告)号：US20130080848A1

公开(公告)日：2013-03-28

申请号：US13680312

申请日：2012-11-19

Applicant: QUALCOMM Incorporated

Inventor： Frederick C. Jen ,  Li Qiu ,  Hsiu C. Ma ,  Calvin V. Ho ,  Xiang M. Song ,  Hsiaohui Wu ,  Thomas E. Little

IPC: G01R31/3177 ,  H03K19/00

CPC classification number: G01R31/3177 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/14 ,  G06F2217/78 ,  H03K19/00

Abstract: A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a circuit includes a combinational logic portion including a logic path including a test isolation gate between a starting element and an ending element. The logic path includes at least a first gate element between the starting element and the test isolation gate. The logic path also includes at least a second gate element between the test isolation gate and the ending element. The starting element and the ending element are coupled to be tested via a scan chain test process during a test mode. In the test mode, an output of the second gate element is fixed at a constant logic level.

Abstract translation: 公开了一种选择要修改为测试隔离门的门的系统和方法。 在特定实施例中，电路包括组合逻辑部分，其包括逻辑路径，逻辑路径包括起始元件和结束元件之间的测试隔离栅极。 逻辑路径至少包括起始元件和测试隔离栅极之间的第一栅极元件。 逻辑路径还包括测试隔离栅极和结束元件之间的至少第二栅极元件。 起始元件和结束元件耦合以在测试模式期间经由扫描链测试过程进行测试。 在测试模式中，第二门元件的输出被固定在恒定的逻辑电平。