公开(公告)号：US08736329B1

公开(公告)日：2014-05-27

申请号：US13760896

申请日：2013-02-06

Applicant: QUALCOMM Incorporated

Inventor： Yashar Rajavi ,  Shahram Abdollahi-Alibeik ,  Hakan Dogan

IPC: H03K3/017

CPC classification number: G06F1/04 ,  H03K5/1565

Abstract: Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.

Abstract translation: 公开了包括具有两个定时器电路以测量时钟信号的脉冲宽度的占空比模块的系统和方法。 两个比较器用于根据脉冲宽度测量的比较来产生控制信号。 响应于控制信号，时钟信号或反相时钟信号可以可编程地延迟，使得时钟信号和反相时钟信号的组合导致校正的时钟信号。 还公开了用于验证占空比模块的操作的系统和方法。