公开(公告)号：US09577639B1

公开(公告)日：2017-02-21

申请号：US14864486

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Bruce Lim ,  Mukul Gupta ,  Hananel Kang ,  Chih-lung Kao ,  Radhika Guttal

IPC: H03K19/0948 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/0948 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract translation: MOS器件包括具有第一MOS晶体管源极，第一MOS晶体管漏极和第一MOS晶体管栅极的第一MOS晶体管。 MOS器件还包括具有第二MOS晶体管源极，第二MOS晶体管漏极和第二MOS晶体管栅极的第二MOS晶体管。 第二MOS晶体管源和第一MOS晶体管源耦合到第一电压源。 MOS器件包括具有第三MOS晶体管栅极的第三MOS晶体管，第一MOS晶体管源极和第三MOS晶体管源极之间的第三MOS晶体管栅极，第三MOS晶体管还具有第三MOS晶体管源极和第三MOS晶体管漏极 所述第三MOS晶体管源耦合到所述第一MOS晶体管源，所述第三MOS晶体管漏极耦合到所述第二MOS晶体管源，所述第三MOS晶体管栅极浮置。