公开(公告)号：US09960231B2

公开(公告)日：2018-05-01

申请号：US15186326

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Satyanarayana Sahu ,  Venugopal Boynapalli

IPC: H01L21/82 ,  H01L29/06 ,  H01L23/535 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

公开(公告)号：US10175571B2

公开(公告)日：2019-01-08

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Ohsang Kwon ,  Mickael Malabry ,  Jingwei Zhang ,  Raymond George Stephany ,  Haining Yang ,  Kern Rim ,  Stanley Seungchul Song ,  Mukul Gupta ,  Foua Vang

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：US09935100B2

公开(公告)日：2018-04-03

申请号：US14936459

申请日：2015-11-09

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Bruce Lim ,  Zhengyu Duan ,  Qi Ye ,  Mickael Malabry

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/45 ,  G06F17/50 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L27/088 ,  G06F17/5072 ,  H01L21/76895 ,  H01L21/823821 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L29/45

Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

公开(公告)号：US20170133365A1

公开(公告)日：2017-05-11

申请号：US14936459

申请日：2015-11-09

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Bruce Lim ,  Zhengyu Duan ,  Qi Ye ,  Mickael Malabry

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/45 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/088 ,  G06F17/5072 ,  H01L21/76895 ,  H01L21/823821 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L29/45

Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

公开(公告)号：US09577639B1

公开(公告)日：2017-02-21

申请号：US14864486

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Bruce Lim ,  Mukul Gupta ,  Hananel Kang ,  Chih-lung Kao ,  Radhika Guttal

IPC: H03K19/0948 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/0948 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract translation: MOS器件包括具有第一MOS晶体管源极，第一MOS晶体管漏极和第一MOS晶体管栅极的第一MOS晶体管。 MOS器件还包括具有第二MOS晶体管源极，第二MOS晶体管漏极和第二MOS晶体管栅极的第二MOS晶体管。 第二MOS晶体管源和第一MOS晶体管源耦合到第一电压源。 MOS器件包括具有第三MOS晶体管栅极的第三MOS晶体管，第一MOS晶体管源极和第三MOS晶体管源极之间的第三MOS晶体管栅极，第三MOS晶体管还具有第三MOS晶体管源极和第三MOS晶体管漏极 所述第三MOS晶体管源耦合到所述第一MOS晶体管源，所述第三MOS晶体管漏极耦合到所述第二MOS晶体管源，所述第三MOS晶体管栅极浮置。