公开(公告)号：US20230046542A1

公开(公告)日：2023-02-16

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar NARALA ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/3206 ,  G06F13/20

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

公开(公告)号：US11625064B2

公开(公告)日：2023-04-11

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar Narala ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3206

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.