公开(公告)号：US20240118902A1

公开(公告)日：2024-04-11

申请号：US18339797

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Erich PLONDKE ,  Hitesh Kumar GUPTA ,  Colin Beaton VERRILLI ,  Rexford Alan HILL

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/30178

Abstract: An aspect of the disclosure relates to a data processing system, including: an input medium configured to include a first set of blocks of data including a first set of block of compressed data and a first set of metadata, respectively; an output medium configured to include a first set of blocks of decompressed data each having a predetermined number of decompressed elements; and a set of single instruction multiple data (SIMD) processors configured to: access the first set of blocks of data from the input medium, respectively; decompress the first set of blocks of compressed data to generate the first set of blocks of decompressed data based on the first set of metadata, respectively; and provide the first set of blocks of decompressed data to the output medium, respectively.

公开(公告)号：US20250021498A1

公开(公告)日：2025-01-16

申请号：US18601341

申请日：2024-03-11

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Hitesh Kumar GUPTA ,  Francisco PEREZ

IPC: G06F13/16

Abstract: A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

公开(公告)号：US20210240394A1

公开(公告)日：2021-08-05

申请号：US17166263

申请日：2021-02-03

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Hitesh Kumar GUPTA ,  Ahmad RADAIDEH

IPC: G06F3/06

Abstract: A device includes a scoreboard and a processor. The scoreboard includes scoreboard entries configured to store information regarding one or more uncompleted memory access operations. The scoreboard also includes a dependency matrix configured to store dependency information corresponding to the scoreboard entries. The processor is configured to retrieve a first memory access instruction that indicates a first address range of a first memory access operation, and to add an indication of the first memory access instruction to a first scoreboard entry. The processor is further configured to, based on determining that the first address range at least partially overlaps a second address range associated with a second scoreboard entry that corresponds to a second memory access instruction, set an element of the dependency matrix to have a has-dependency value indicating a dependency of the first scoreboard entry on the second scoreboard entry.