公开(公告)号：US20190067178A1

公开(公告)日：2019-02-28

申请号：US15690541

申请日：2017-08-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Layal Rouhana

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: Some features pertain to a substrate that includes a first dielectric, a first interconnect, and a second interconnect. The first interconnect is at least partially embedded in the first dielectric layer. The first interconnect includes a first portion and a second portion. The first portion is configured to increase reliability as compared to a substrate having only a second portion of a first interconnect. The increase in reliability due at least in part to the first portion providing additional interconnect material to mitigate interconnect material lost through electromigration. A part of the second portion (of the first interconnect) is free of the first dielectric and may be configured to be coupled to another device.

公开(公告)号：US10651160B2

公开(公告)日：2020-05-12

申请号：US15867518

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Christopher Bahr ,  Layal Rouhana

IPC: H01L21/48 ,  H01L23/49 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.

公开(公告)号：US10157824B2

公开(公告)日：2018-12-18

申请号：US15678698

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Layal Rouhana ,  Seongryul Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

公开(公告)号：US10804195B2

公开(公告)日：2020-10-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Marcus Hsu ,  Brigham Navaja ,  Houssam Jomaa

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.