公开(公告)号：US11456291B2

公开(公告)日：2022-09-27

申请号：US16910486

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

公开(公告)号：US10804195B2

公开(公告)日：2020-10-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Marcus Hsu ,  Brigham Navaja ,  Houssam Jomaa

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

公开(公告)号：US11527498B2

公开(公告)日：2022-12-13

申请号：US17038124

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Michelle Yejin Kim ,  Marcus Hsu

IPC: H01L23/00

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

公开(公告)号：US20210407979A1

公开(公告)日：2021-12-30

申请号：US16910486

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

公开(公告)号：US20210280523A1

公开(公告)日：2021-09-09

申请号：US16916339

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Marcus Hsu ,  David Fraser Rae

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other exemplary aspects, the top and bottom metallization structures can include redistribution layers (RDLs) to provide increased electrical conductivity between die interconnects and substrate interconnects.

公开(公告)号：US11784151B2

公开(公告)日：2023-10-10

申请号：US16936263

申请日：2020-07-22

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Marcus Hsu

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2924/01029 ,  H01L2924/30101

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

公开(公告)号：US11682607B2

公开(公告)日：2023-06-20

申请号：US17164729

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L21/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/14051

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US11552023B2

公开(公告)日：2023-01-10

申请号：US16913288

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Brigham Navaja ,  Marcus Hsu ,  Terence Cheung

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L21/48 ,  H01L49/02

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.