公开(公告)号：US11626865B1

公开(公告)日：2023-04-11

申请号：US17481666

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jianwen Ye ,  Bo Sun ,  Cheng Zhong

IPC: H03K5/01 ,  H03K19/20 ,  H03L7/081 ,  H03K5/00 ,  H04B1/40 ,  H04L12/40

Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.