公开(公告)号：US11823043B2

公开(公告)日：2023-11-21

申请号：US16688602

申请日：2019-11-19

申请人： QUALCOMM Incorporated

发明人： Jonathan Dewitt Wolfe ,  Erich Plondke

IPC分类号： G06N3/00 ,  G06N3/08 ,  G06F7/556 ,  G06F17/14 ,  G06N3/04

CPC分类号： G06N3/08 ,  G06F7/556 ,  G06F17/14 ,  G06N3/04

摘要： Aspects described herein provide a method of processing data in a machine learning model, including: receiving first domain input data; transforming the first domain input data to second domain input data via a domain transformation function; providing the second domain input data to a first layer of a machine learning model; processing the second domain input data in the first layer of the machine learning model according to a set of layer weights; and outputting second domain output data from the first layer of the machine learning model.

公开(公告)号：US12086636B2

公开(公告)日：2024-09-10

申请号：US17463393

申请日：2021-08-31

申请人： QUALCOMM Incorporated

发明人： Jonathan Dewitt Wolfe ,  Erich Plondke

IPC分类号： G06F9/50 ,  G06F8/41 ,  G06F9/48

CPC分类号： G06F9/5027 ,  G06F8/433 ,  G06F8/445 ,  G06F9/4881

摘要： Certain aspects of the present disclosure provide techniques for generating execution schedules, comprising receiving a data flow graph for a process, where data flow graph comprises a plurality of nodes and a plurality of edge; generating a topological ordering for the data flow graph based at least in part on memory utilization of the process; generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity; allocating units of memory in the memory based on the first modified topological ordering; and generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, where the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.