公开(公告)号：US09225324B2

公开(公告)日：2015-12-29

申请号：US14257913

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Arcudia ,  Zhiqin Chen

IPC: H03M9/00 ,  H03K5/156 ,  H03L7/06

CPC classification number: H03K5/1565 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0812 ,  H03M9/00

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract translation: 公开了用于产生具有精确定时关系的时钟相位信号的系统和方法。 例如，可以从差分CML时钟信号产生间隔90度的四个时钟信号。 CML到CMOS转换器将差分CML时钟信号转换为差分CMOS时钟信号，并提供占空比校正。 延迟单元从差分CMOS时钟信号产生延迟的时钟信号。 差分CMOS时钟信号和延迟的时钟信号被逻辑地组合以产生具有四分之一时钟周期的有效时间的四分之四四个时钟信号。 设置复位锁存器从四分之一时钟信号产生四个时钟信号。 校准模块控制延迟单元的延迟，并控制CML到CMOS转换器的占空比校正，以调整四个时钟信号的时序关系。 四个时钟信号可以例如在解串器中使用。

公开(公告)号：US20150303909A1

公开(公告)日：2015-10-22

申请号：US14257913

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Arcudia ,  Zhiqin Chen

IPC: H03K5/156 ,  H03M9/00 ,  H03L7/06

CPC classification number: H03K5/1565 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0812 ,  H03M9/00

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract translation: 公开了用于产生具有精确定时关系的时钟相位信号的系统和方法。 例如，可以从差分CML时钟信号产生间隔90度的四个时钟信号。 CML到CMOS转换器将差分CML时钟信号转换为差分CMOS时钟信号，并提供占空比校正。 延迟单元从差分CMOS时钟信号产生延迟的时钟信号。 差分CMOS时钟信号和延迟的时钟信号被逻辑地组合以产生具有四分之一时钟周期的有效时间的四分之四四个时钟信号。 设置复位锁存器从四分之一时钟信号产生四个时钟信号。 校准模块控制延迟单元的延迟，并控制CML到CMOS转换器的占空比校正，以调整四个时钟信号的时序关系。 四个时钟信号可以例如在解串器中使用。