公开(公告)号：US20250103130A1

公开(公告)日：2025-03-27

申请号：US18475371

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Matthew Severson ,  Gabriel Watkins ,  Vijayakumar Ashok Dibbad ,  Ronald Alton ,  Lai Xu ,  Jeffrey Gemar

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.