公开(公告)号：US20170046167A1

公开(公告)日：2017-02-16

申请号：US14863612

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Luke Yen ,  Michael William Morrow ,  Jeffery Michael Schottmiller ,  James Norris Dieffenderfer

IPC: G06F9/38 ,  G06F9/30

Abstract: Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT) are disclosed. In one aspect, an instruction processing circuit accesses a PAT containing entries each comprising an address of a memory instruction. Upon detecting a memory instruction in an instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If so, the instruction processing circuit prevents the detected memory instruction from taking effect before at least one pending memory instruction older than the detected memory instruction, to preempt a memory instruction punt. In some aspects, the instruction processing circuit may determine, upon execution of a pending memory instruction, whether a hazard associated with the detected memory instruction has occurred. If so, an entry for the detected memory instruction is generated in the PAT.

Abstract translation: 公开了使用平底逃避表（PAT）预测计算机处理器中的存储器指令平移。 在一个方面，指令处理电路访问包含条目的PAT，每个条目包括存储器指令的地址。 在检测到指令流中的存储器指令时，指令处理电路确定PAT是否包含具有存储器指令地址的条目。 如果是这样，则指令处理电路防止检测到的存储器指令在比检测到的存储器指令之前的至少一个未决存储器指令之前生效，以抢占存储器指令punt。 在一些方面，指令处理电路可以在执行待决存储器指令时确定是否已经发生与检测到的存储器指令相关联的危险。 如果是，则在PAT中生成检测到的存储器指令的条目。

公开(公告)号：US20200097296A1

公开(公告)日：2020-03-26

申请号：US16138011

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Rodney Wayne Smith ,  Yusuf Cagatay Tekmen ,  Luke Yen

IPC: G06F9/38 ,  G06F9/30 ,  G06F5/06

Abstract: Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture is provided. In this regard, an OOP-based device provides a register management circuit that is configured to employ a combination of the checkpoint approach and the virtual register approach. The register management circuit includes a most recent table (MRT) for tracking mappings of logical register numbers (LRNs) to physical register numbers (PRNs), a physical register file (PRF) storing information for physical registers, a virtual register file (VRF) storing data for virtual registers, and a checkpoint queue for tracking active checkpoints (each of which is a snapshot of the MRT at a given time). The register management circuit applies checkpoint selection criteria for balancing the number of checkpoints, and implements late physical register allocation using virtual registers to provide an effectively larger physical register file and checkpoint-based early release of physical registers.

公开(公告)号：US11669333B2

公开(公告)日：2023-06-06

申请号：US15963126

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Rodney Wayne Smith ,  Raghavan Madhavan ,  Luke Yen ,  Shivam Priyadarshi ,  Yusuf Cagatay Tekmen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3802

Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

公开(公告)号：US10860328B2

公开(公告)日：2020-12-08

申请号：US16138011

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Rodney Wayne Smith ,  Yusuf Cagatay Tekmen ,  Luke Yen

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F5/06 ,  G06F9/30

Abstract: Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture is provided. In this regard, an OOP-based device provides a register management circuit that is configured to employ a combination of the checkpoint approach and the virtual register approach. The register management circuit includes a most recent table (MRT) for tracking mappings of logical register numbers (LRNs) to physical register numbers (PRNs), a physical register file (PRF) storing information for physical registers, a virtual register file (VRF) storing data for virtual registers, and a checkpoint queue for tracking active checkpoints (each of which is a snapshot of the MRT at a given time). The register management circuit applies checkpoint selection criteria for balancing the number of checkpoints, and implements late physical register allocation using virtual registers to provide an effectively larger physical register file and checkpoint-based early release of physical registers.