公开(公告)号：US11900111B2

公开(公告)日：2024-02-13

申请号：US17448816

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Srijesh Sudarsanan ,  Deepak Mathew ,  Marc Hoffman ,  Gerald Sweeney ,  Sundar Rajan Balasubramanian ,  Hongfeng Dong ,  Yurong Sun ,  Seyedmehdi Sadeghzadeh

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30101

Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

公开(公告)号：US12159140B2

公开(公告)日：2024-12-03

申请号：US17732361

申请日：2022-04-28

Applicant: QUALCOMM Incorporated

Inventor： Srijesh Sudarsanan ,  Deepak Mathew ,  Marc Hoffman ,  Sundar Rajan Balasubramanian ,  Mansi Jain ,  James Lee ,  Gerald Sweeney

IPC: G06F9/30 ,  G06N3/04

Abstract: An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.

公开(公告)号：US20230097103A1

公开(公告)日：2023-03-30

申请号：US17448810

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Santosh Srivatsan Srinivasan ,  Marc Hoffman ,  Srijesh Sudarsanan ,  Deepak Mathew ,  Hongfeng Dong ,  Gerald Sweeney

IPC: G06F17/14 ,  G06F9/30

Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.

公开(公告)号：US10466967B2

公开(公告)日：2019-11-05

申请号：US15224237

申请日：2016-07-29

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Yurong Sun ,  Jianming Zhu ,  Marc Hoffman

IPC: G06F7/483 ,  G06F17/17 ,  G06F9/30 ,  G06F7/544 ,  G06F1/03 ,  G06F7/548

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

公开(公告)号：US20180032311A1

公开(公告)日：2018-02-01

申请号：US15224237

申请日：2016-07-29

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Ajay Anant Ingle ,  Yurong Sun ,  Jianming Zhu ,  Marc Hoffman

IPC: G06F7/483

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.