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公开(公告)号:US20180136680A1
公开(公告)日:2018-05-17
申请号:US15854597
申请日:2017-12-26
Applicant: QUALCOMM Incorporated
Inventor: Mengmeng DU , Hua GUAN , Ngai Yeung HO , Chi Fan YUNG
Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
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公开(公告)号:US20170322575A1
公开(公告)日:2017-11-09
申请号:US15256315
申请日:2016-09-02
Applicant: QUALCOMM Incorporated
Inventor: Mengmeng DU , Hua GUAN , Ngai Yeung HO , Chi Fan YUNG
IPC: G05F1/575
Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
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公开(公告)号:US20180120879A1
公开(公告)日:2018-05-03
申请号:US15438605
申请日:2017-02-21
Applicant: QUALCOMM Incorporated
Inventor: Mengmeng DU , Hua GUAN
IPC: G05F1/575
Abstract: A voltage regulation circuit improves power supply rejection ratio and load-transient performance. The voltage regulation circuit includes a low dropout (LDO) voltage regulator and an inverting amplifier stage. The LDO voltage regulator includes a first error amplifier and a power field effect transistor (FET). The first error amplifier includes a first input and a second input. The second input receives an output signal fed back from the LDO voltage regulator. The inverting amplifier stage includes an output terminal coupled to the first input of the first error amplifier. The inverting amplifier stage also includes a first input that receives the output fed back from the LDO voltage regulator and a second input that receives a reference voltage.
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