公开(公告)号：US20240411968A1

公开(公告)日：2024-12-12

申请号：US18332416

申请日：2023-06-09

Applicant: QUALCOMM Incorporated

Inventor： Gokce SARAR ,  Ryan Michael CAREY ,  Arnav BALLANI ,  Bernard BOURON ,  Chandram KOTTURI ,  Chin-Wei HSU ,  Akshay Sanjay SARODE ,  Romain LEPERT ,  Michael DEFFERRARD ,  Onur ATAN ,  Lindsey Makana KOSTAS

IPC: G06F30/327

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for evaluating electronic circuit designs. A directed graph representing a netlist design for an electrical circuit is accessed, the netlist design comprising a plurality of electronic components and a plurality of connections among the plurality of electronic components. A node in the directed graph is selected, the node corresponding to a register that receives input from one or more of the plurality of electronic components in the netlist design. A subgraph is generated for the node, based on the directed graph, comprising identifying a connectivity cone ending at the first register. A functional embedding is generated for the subgraph based on a trained encoder machine learning model. A predicted performance characteristic of the netlist design is generated based at least in part on the functional embedding.