公开(公告)号：US20250094182A1

公开(公告)日：2025-03-20

申请号：US18469630

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Sneha Wani ,  Mohd Imran Beg ,  Nitin Makhija ,  Arun Sukheja

IPC: G06F9/448

Abstract: Performing dynamic microarchitectural throttling of processor cores based on Quality-of-Service (QOS) levels in processor devices is disclosed herein. In some aspects, a processor device comprises a synchronous core cluster including a plurality of processor cores, a throttling selection circuit, and a throttling circuit. The throttling selection circuit receives a QoS level associated with a workload scheduled for execution by a processor core. The throttling selection circuit determines a performance state of the processor core, and determines a throttling level for the processor core, based on the QoS level and the performance state. The throttling selection circuit provides the throttling level to the throttling circuit, which performs microarchitectural throttling of the processor core based on the throttling level.