公开(公告)号：US12093155B2

公开(公告)日：2024-09-17

申请号：US17448864

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Bohuslav Rychlik ,  Niraj Shantilal Paliwal

IPC: G06F11/30 ,  G06F7/544 ,  G06F9/50 ,  G06F11/07 ,  G06N3/048

CPC classification number: G06F11/302 ,  G06F7/5443 ,  G06F9/5066 ,  G06F11/0772 ,  G06N3/048

Abstract: Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.