公开(公告)号：US11063617B1

公开(公告)日：2021-07-13

申请号：US16869898

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Mohamed Abouzied ,  Ibrahim Ramez Chamas ,  Bhushan Shanti Asuri ,  Osama Elhadidy

IPC: H03D7/10 ,  H03D7/12 ,  H04B1/00 ,  H03F3/21

Abstract: Certain aspects provide a circuit for frequency conversion. The circuit includes first mixer circuitry coupled to a load circuit and having a first mixer configured to generate a first portion of a frequency-converted differential signal to be provided to the load circuit based on first differential input signals and second differential input signals, and a second mixer configured to generate a second portion of the frequency-converted differential signal based on third differential input signals and fourth differential input signals. The circuit also includes second mixer circuitry coupled to another load circuit and having a third mixer configured to generate a first portion of another frequency-converted differential signal based on the first differential input signals and the fourth differential input signals, and a fourth mixer configured to generate a second portion of the other frequency-converted differential signal based on the third differential input signals and the second differential input signals.

公开(公告)号：US12113499B2

公开(公告)日：2024-10-08

申请号：US18068837

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Peter Gazzerro ,  Nitz Saputra ,  Ashok Swaminathan ,  Osama Elhadidy ,  Bo Yang

IPC: H03H11/04 ,  H03M1/06 ,  H03M1/66 ,  H04B1/04

CPC classification number: H03H11/0461 ,  H03M1/0626 ,  H03M1/66 ,  H04B1/04

Abstract: Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.