公开(公告)号：US20220068370A1

公开(公告)日：2022-03-03

申请号：US17008433

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Percy DADABHOY

IPC: G11C11/418 ,  G11C11/419 ,  G11C11/412 ,  H04M1/2745

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.

公开(公告)号：US20210098057A1

公开(公告)日：2021-04-01

申请号：US16911313

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Chulmin JUNG ,  Percy DADABHOY

IPC: G11C11/419 ,  H03K3/3562 ,  H04M1/02

Abstract: A memory is provided with a pre-charge circuit/write driver that pre-charges a bit line in a bit line pair responsive to a master latch output signal from a master latch in a data buffer. A slave latch associated with the master latch is prevented from becoming open by a clock controller during write operations for the memory.

公开(公告)号：US20220068373A1

公开(公告)日：2022-03-03

申请号：US17008476

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Percy DADABHOY ,  Arun Babu PALLERLA

IPC: G11C11/419

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. To assist the charge-transfer by the charge-transfer transistor, a first and second cross-coupled transistor are coupled between the bit line and a complement bit line.