公开(公告)号：US20230170000A1

公开(公告)日：2023-06-01

申请号：US17456773

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Anil Chowdary KOTA ,  Changho JUNG ,  Chulmin JUNG

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C7/106 ,  G11C7/1087 ,  G11C7/1063 ,  G11C7/12 ,  G11C5/14

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

公开(公告)号：US20220068370A1

公开(公告)日：2022-03-03

申请号：US17008433

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Percy DADABHOY

IPC: G11C11/418 ,  G11C11/419 ,  G11C11/412 ,  H04M1/2745

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.

公开(公告)号：US20200335151A1

公开(公告)日：2020-10-22

申请号：US16849616

申请日：2020-04-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Keejong KIM ,  Changho JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge-transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

公开(公告)号：US20220199152A1

公开(公告)日：2022-06-23

申请号：US17131172

申请日：2020-12-22

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418 ,  G06F3/06

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.

公开(公告)号：US20220093171A1

公开(公告)日：2022-03-24

申请号：US17028965

申请日：2020-09-22

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US20210134358A1

公开(公告)日：2021-05-06

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Keejong KIM ,  Chulmin JUNG ,  Ritu CHABA

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US20170075379A1

公开(公告)日：2017-03-16

申请号：US14855319

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu KWOK ,  Nishith Nitin DESAI ,  Changho JUNG

IPC: G06F1/12 ,  G06F3/06

CPC classification number: G06F3/0683 ,  G06F3/0611 ,  G06F3/0659 ,  G06F13/1689 ,  G11C7/1075 ,  G11C7/22 ,  G11C11/419

Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.

Abstract translation: 公开了用于访问存储器的存储器和方法的方面。 存储器包括多个存储器单元，其被配置为在第一模式的存储器循环中支持读和写操作，并且在第二模式中在存储器循环中支持只读操作。 存储器还包括控制电路，其被配置为产生用于读取操作的读取时钟和用于写入操作的写入时钟。 写时钟的定时是第一模式中的读时钟的定时和第二模式中的存储器周期的定时的函数。

公开(公告)号：US20230307020A1

公开(公告)日：2023-09-28

申请号：US17702770

申请日：2022-03-23

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Anil Chowdary KOTA ,  Changho JUNG

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/08 ,  G11C8/08

CPC classification number: G11C7/222 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/1009 ,  G11C7/08 ,  G11C8/08

Abstract: A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

公开(公告)号：US20180012649A1

公开(公告)日：2018-01-11

申请号：US15206018

申请日：2016-07-08

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Changho JUNG

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/418

Abstract: A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.

公开(公告)号：US20150294694A1

公开(公告)日：2015-10-15

申请号：US14251495

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Tony Chung Yiu KWOK ,  Nishith Nitin DESAI

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C5/063 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/11807 ,  H01L2027/11838

Abstract: A CMOS apparatus includes a first transistor having a first transistor gate, a second transistor having a second transistor gate, a partial transistor having a gate and only one of a drain or a source. The CMOS apparatus further includes a gate interconnect connecting the first transistor gate to the second transistor gate through the gate of the partial transistor. The CMOS apparatus may be a bit cell. A write word enable line may include the gate interconnect, and the first and second transistors may enable write bit lines to the bit cell.

Abstract translation: CMOS器件包括具有第一晶体管栅极的第一晶体管，具有第二晶体管栅极的第二晶体管，具有栅极且仅漏极或源极之一的部分晶体管。 CMOS器件还包括通过部分晶体管的栅极将第一晶体管栅极连接到第二晶体管栅极的栅极互连。 CMOS装置可以是位单元。 写字使能线可以包括栅极互连，并且第一和第二晶体管可以使能到位单元的写位线。