公开(公告)号：US11736105B1

公开(公告)日：2023-08-22

申请号：US17831306

申请日：2022-06-02

Applicant: QUALCOMM Incorporated

Inventor： Abhinav Murali ,  Pradeep Kumar Sana ,  Sajin Mohamad ,  Harikrishna Chintarlapalli Reddy ,  Rakesh Kumar Sinha ,  Jibu Varghese K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

公开(公告)号：US12057829B2

公开(公告)日：2024-08-06

申请号：US18336621

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Abhinav Murali ,  Pradeep Kumar Sana ,  Sajin Mohamad ,  Harikrishna Chintarlapalli Reddy ,  Rakesh Kumar Sinha ,  Jibu Varghese K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.