公开(公告)号：US20160004617A1

公开(公告)日：2016-01-07

申请号：US14323916

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Hari Madhava Rao ,  Joseph Weizhou Fang ,  Sami Khawam ,  Ioannis Nousias ,  Raju Macha ,  Ihab Abdelmuti ,  Venugopal Boynapalli

IPC: G06F11/22 ,  G06F13/40

CPC classification number: G06F11/2289 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/263 ,  G06F13/4022

Abstract: An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals.

Abstract translation: 提供了包括瓦片阵列的指令单元阵列。 每个瓦片包括用于在多个输入通道和多个相应的输出通道之间切换的一组输入/输出（I / O）端口。 此外，每个瓦片包括指令单元，该指令单元包括多个专用逻辑门，用于产生从瓦片的输入通道中的选定的输入通道输出的指令单元。 每个I / O端口被配置为从瓦片的指令单元输出和输入通道中选择用于瓦片的剩余I / O端口以形成I / O端口的输出通道。 为了在阵列的自动测试模式生成（ATPG）期间防止组合循环，本文公开的指令单元阵列被配置在测试模式中，使得每个瓦片的I / O端口的至少一个子集阻止其任何输出通道 被形成为组合信号。