公开(公告)号：US10122168B2

公开(公告)日：2018-11-06

申请号：US15269893

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Ricardo Goncalves ,  Joshua Zazzera ,  Edgar Marti-Arbona ,  Juha Oikarinen ,  Joseph Rutkowski

IPC: H02J3/00 ,  G05F1/10 ,  H02M1/088 ,  H02M3/158 ,  G06F1/32 ,  H02J7/00 ,  H02M1/00

Abstract: An apparatus and method for to incrementally reduce (e.g., de-rate) a power supply voltage output (VOUT) of a regulator to multiple subsystems in response to detecting high power conditions in a client device is described. In one instance, multiple low power client devices and a high power consumption client device are coupled to a power grid of the power management system with a power management integrated circuit (PMIC) supplying power to the power grid. The PMIC includes a buck-or-boost switching regulator including a load current adjustment device to de-rate the high power consumption device when a sum of the current consumed by the high power consumption device and the low power client devices is above a predetermined threshold.

公开(公告)号：US11817771B2

公开(公告)日：2023-11-14

申请号：US17319749

申请日：2021-05-13

Applicant: QUALCOMM Incorporated

Inventor： Troy Stockstad ,  Gianluca Valentino ,  Ricardo Goncalves

IPC: H02M1/08 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M1/08 ,  H02M1/0006 ,  H02M3/158

Abstract: Techniques and apparatus for driving a transistor gate of a switched-mode power supply (SMPS) circuit. One example gate driver for a switching transistor of an SMPS circuit generally includes a first power supply rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating supply node; a pulldown transistor having a drain coupled to the output node of the gate driver and having a source coupled to the reference rail; and a pulldown logic buffer having a first power supply input coupled to the floating supply node, having a second power supply input coupled to the reference rail, and having an output coupled to a gate of the pulldown transistor. The floating supply node is configured to selectively receive power from the first power supply rail and the output node of the gate driver.