公开(公告)号：US20170371783A1

公开(公告)日：2017-12-28

申请号：US15191686

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Eric Francis Robinson ,  Brad Herold ,  Robert Bell, JR.

IPC: G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/084 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/167 ,  G06F2212/1024 ,  G06F2212/272

Abstract: Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system is disclosed. A shared cache memory system is provided comprising local shared cache memories accessible by an associated central processing unit (CPU) and other CPUs in a peer-to-peer manner. When a CPU desires to request a cache transfer (e.g., in response to a cache eviction), the CPU acting as a master CPU issues a cache transfer request. In response, target CPUs issue snoop responses indicating their willingness to accept the cache transfer. The target CPUs also use the snoop responses to be self-aware of the willingness of other target CPUs to accept the cache transfer. The target CPUs willing to accept the cache transfer use a predefined target CPU selection scheme to determine its acceptance of the cache transfer. This can avoid a CPU making multiple requests to find a target CPU for a cache transfer.