公开(公告)号：US07970999B2

公开(公告)日：2011-06-28

申请号：US12009955

申请日：2008-01-22

申请人： Robert C Duzett

发明人： Robert C Duzett

IPC分类号： G06F12/00

CPC分类号： G06F12/0813 ,  G06F17/30902 ,  G06F2212/272 ,  H04L67/2852

摘要： An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data processing node also includes interface logic configured to receive signals from the interconnect and to apply the signals from the interconnect to affect the content of the cache, and to receive signals from the mass storage and to apply the signals from the mass storage to affect the content of the cache. The content of the mass storage and cache of a particular node may also be provided to other nodes of the system, via the interconnect.

摘要翻译： 信息分发系统包括耦合到互连的互连和多个数据处理节点。 每个数据处理节点包括大容量存储和高速缓存。 每个数据处理节点还包括接口逻辑，其被配置为从互连接收信号并且施加来自互连的信号以影响高速缓存的内容，并且从大容量存储接收信号并且应用来自大容量存储的信号以影响 缓存的内容。 特定节点的大容量存储和高速缓存的内容也可以经由互连提供给系统的其他节点。

公开(公告)号：US06631449B1

公开(公告)日：2003-10-07

申请号：US09972831

申请日：2001-10-05

申请人： Paul L. Borrill

发明人： Paul L. Borrill

IPC分类号： G06F1208

CPC分类号： G06F12/0813 ,  G06F12/0824 ,  G06F2212/272

摘要： A system and method for maintaining storage object consistency across a distributed storage network including a migratable repository of last resort which stores a last or only remaining data replica that may not be deleted. The method includes the steps of monitoring data requests to the repository of last resort, deciding whether to move the repository of last resort, and migrating the repository of last resort.

摘要翻译： 一种用于在分布式存储网络中维护存储对象一致性的系统和方法，包括最后的手段的可迁移存储库，其存储可能不被删除的最后或仅剩余的数据副本。 该方法包括以下步骤：监控最后访问库的数据请求，决定是否移动最后的存储库，以及迁移最后的存储库。

公开(公告)号：US20030177316A1

公开(公告)日：2003-09-18

申请号：US10409508

申请日：2003-04-08

申请人： Broadcom Corporation

发明人： Joseph B. Rowlands ,  Michael D. Carlson

IPC分类号： G06F012/00

CPC分类号： G06F12/0817 ,  G06F2212/272

摘要： An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.

摘要翻译： 响应于对共享块的写入，代理被配置为在代理通信的接口上发起读独占事务。 另外，代理被配置为向响应代理或接口上的代理指示响应于所读取的独占事务而不需要来自响应代理或代理的数据传输。 在一个实施例中，代理向响应代理指示在事务的响应阶段中不需要数据传送。 具体地，代理可以以这样的方式进行响应，即代理人指示它将提供数据（即代理将向其自己提供数据）。 例如，代理可以用独占所有权指示进行响应。 在这种实施例的接口上，独占所有权响应可以要求具有独占访问的代理响应数据。

公开(公告)号：US06571321B2

公开(公告)日：2003-05-27

申请号：US09917432

申请日：2001-07-27

申请人： Joseph B. Rowlands ,  Michael D. Carlson

发明人： Joseph B. Rowlands ,  Michael D. Carlson

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/272

摘要： An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.

摘要翻译： 响应于对共享块的写入，代理被配置为在代理通信的接口上发起读独占事务。 另外，代理被配置为向响应代理或接口上的代理指示响应于所读取的独占事务而不需要响应代理或代理的数据传输。 在一个实施例中，代理向响应代理指示在事务的响应阶段中不需要数据传送。 具体地，代理可以以这样的方式进行响应，即代理人指示它将提供数据（即代理将向其自己提供数据）。 例如，代理可以用独占所有权指示进行响应。 在这种实施例的接口上，独占所有权响应可以要求具有独占访问的代理响应数据。

公开(公告)号：US20020078310A1

公开(公告)日：2002-06-20

申请号：US09967404

申请日：2001-09-28

申请人： Sun Microsystems, Inc.

发明人： Steven J. Frank ,  Henry Burkhardt III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

IPC分类号： G06F012/00

CPC分类号： G06F9/5016 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0833 ,  G06F12/10 ,  G06F12/1018 ,  G06F12/126 ,  G06F2212/272 ,  H04L12/4637 ,  H04L45/04

摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

摘要翻译： 多处理器数字数据处理系统包括以环的分层布置的多个处理单元。 系统选择性地分配存储并且响应于由单元产生的访问请求而将独占数据副本从单元移动到单元。 采用路由元素来选择性地广播环上的数据访问请求，更新和传送。

公开(公告)号：US20020078309A1

公开(公告)日：2002-06-20

申请号：US09740218

申请日：2000-12-19

申请人： International Business Machines Corporation

发明人： Ravi Kumar Arimilli ,  James Stephen Fields JR. ,  Sanjeev Ghai ,  Jody Bern Joyner

IPC分类号： G06F013/00

CPC分类号： G06F12/0811 ,  G06F2212/272

摘要： An apparatus for associating cache memories with processors within a multiprocessor data processing system is disclosed. The multiprocessor data processing system includes multiple processing units and multiple cache memories. Each of the cache memories includes a cache memory controller, and each cache memory controller includes a mode register. Each mode register has multiple processing unit fields, and each of the processing unit fields is associated with one of the processing units for indicating whether or not data from an associated processing unit should be cached by a cache memory associated to a corresponding cache memory controller.

摘要翻译： 公开了一种用于将高速缓冲存储器与多处理器数据处理系统中的处理器相关联的装置。 多处理器数据处理系统包括多个处理单元和多个高速缓冲存储器。 每个高速缓存存储器包括高速缓冲存储器控制器，并且每个高速缓冲存储器控制器包括模式寄存器。 每个模式寄存器具有多个处理单元字段，并且每个处理单元字段与处理单元之一相关联，用于指示来自相关处理单元的数据是否应由与对应的高速缓冲存储器控制器相关联的高速缓冲存储器缓存。

公开(公告)号：US20010042176A1

公开(公告)日：2001-11-15

申请号：US09148820

申请日：1998-09-04

发明人： ERIK E. HAGERSTEN ,  MARK HILL

IPC分类号： G06F012/08

CPC分类号： G06F11/0712 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F12/0284 ,  G06F12/0864 ,  G06F12/1018 ,  G06F12/1072 ,  G06F2212/2542 ,  G06F2212/272

摘要： A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copies to local memory space of a node such that accesses to the data may be performed locally rather than globally. The copies data is referred to as a shadow page. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, the page to which shadow copies may be stored and which global addresses may be converted to local physical addresses may be restricted. Multiple page of local memory space may be allocated to one entry of a local physical address to global address (LPA2GA) table. When a page is allocated to store shadow pages, an entry in the LPA2GA table associated with that page is marked as unavailable. Accordingly, new translations may not be stored to that entry of the LPA2GA table and other pages associated with that entry may not be allocated to store shadow pages. In a similar manner, multiple pages of the global address space are mapped to an entry in a global address to local physical address (GA2LPA) translation table. When data corresponding to a page within the global address space is stored as a shadow page, the entry associated with the global address is marked as unavailable. Accordingly, other pages associated with that entry of the GA2LPA table may not be stored as shadow pages because the entry is not available. The local copy of the data is not stored and the node must access the data globally. To decrease the probability that an entry is not available for a page, the GA2LPA table may be implemented as a set associative table. To further increase the availability of entries in the GA2LPA table, a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

公开(公告)号：US5822578A

公开(公告)日：1998-10-13

申请号：US461166

申请日：1995-06-05

申请人： Steven Frank ,  Henry Burkhardt, III ,  Frederick D. Weber ,  Linda Q. Lee ,  John A. Roskosz ,  Brett D. Byers ,  Peter C. Schnorr ,  David I. Epstein

发明人： Steven Frank ,  Henry Burkhardt, III ,  Frederick D. Weber ,  Linda Q. Lee ,  John A. Roskosz ,  Brett D. Byers ,  Peter C. Schnorr ,  David I. Epstein

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56 ,  G06F9/00

CPC分类号： G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/10 ,  G06F9/3005 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272

摘要： Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. Inserted-instructions are executed by the first processor in the same manner as, and without affecting the sequence of, instructions from the first instruction source. The first instruction source can be a memory element, including an instruction cache element for storing digital values representative of instructions and program steps, or an execution unit (CEU) which asserts signals to the instruction cache element to cause instructions to be transmitted to the CEU. The processors include input/output (I/O) processors having direct memory access (DMA) insert elements, which respond to a peripheral device to generate DMA inserted-instructions. These DMA inserted-instructions are executable by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.

摘要翻译： 数字多处理器方法和装置包括多个处理器，包括用于正常处理包括来自第一指令源的指令的指令流的第一处理器。 至少一个处理器可以将插入的指令发送到第一处理器。 插入指令以与第一指令源相同的方式由第一处理器执行，而不影响来自第一指令源的指令序列。 第一指令源可以是存储元件，包括用于存储表示指令和程序步骤的数字值的指令高速缓存元件，或者执行单元（CEU），其向指令高速缓存元件发出信号以使指令被发送到CEU 。 处理器包括具有直接存储器访问（DMA）插入元件的输入/输出（I / O）处理器，其响应于外围设备以产生DMA插入指令。 这些DMA插入指令可以由第一处理元件以与来自第一指令源的指令的处理顺序相同的方式执行，并且不影响来自第一指令源的指令的处理顺序。

公开(公告)号：US5710907A

公开(公告)日：1998-01-20

申请号：US577283

申请日：1995-12-22

申请人： Erik Hagersten ,  Robert C. Zak, Jr.

发明人： Erik Hagersten ,  Robert C. Zak, Jr.

IPC分类号： G06F12/08 ,  G06F13/14

CPC分类号： G06F12/0813 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/2542 ,  G06F2212/272

摘要： The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access. Conversely, when caching in NUMA mode, the sub-system stores the data, typically a line of data, in its hybrid cache.

公开(公告)号：US20110153953A1

公开(公告)日：2011-06-23

申请号：US12645855

申请日：2009-12-23

申请人： Prakash Khemani ,  Anil Kumar ,  Abhishek Chauhan ,  Rama Praveen

发明人： Prakash Khemani ,  Anil Kumar ,  Abhishek Chauhan ,  Rama Praveen

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0895 ,  G06F12/0815 ,  G06F2212/272

摘要： A multi-core system that includes a 64-bit cache storage and a 32-bit memory storage that stores a 32-bit cache object directory. One or more cache engines execute on cores of the multi-core system to retrieve objects from the 64-bit cache, create cache directory objects, insert the created cache directory object into the cache object directory, and search for cache directory objects in the cache object directory. When an object is stored in the 64-bit cache, a cache engine can create a cache directory object that corresponds to the cached object and can insert the created cache directory object into an instance of a cache object directory. A second cache engine can receive a request to access the cached object and can identify a cache directory object in the instance of the cache object directory, using a hash key calculated based on one or more attributes of the cached object.

摘要翻译： 包含64位高速缓存存储器和32位存储器的多核系统，用于存储32位缓存对象目录。 在多核系统的核心上执行一个或多个缓存引擎，以从64位缓存中检索对象，创建缓存目录对象，将创建的缓存目录对象插入到缓存对象目录中，并在高速缓存中搜索缓存目录对象 对象目录。 当对象存储在64位高速缓存中时，缓存引擎可以创建与缓存对象相对应的缓存目录对象，并将创建的高速缓存目录对象插入到缓存对象目录的实例中。 第二缓存引擎可以接收访问缓存对象的请求，并且可以使用基于缓存对象的一个​​或多个属性计算的散列密钥来识别缓存对象目录的实例中的高速缓存目录对象。