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公开(公告)号:US11481865B2
公开(公告)日:2022-10-25
申请号:US17173643
申请日:2021-02-11
Applicant: QUALCOMM Incorporated
Inventor: Elina Kamenetskaya , Liang Li , Andrew Evan Gruber , Jeffrey Leger , Balaji Calidas , Ruihao Zhang
IPC: G06T1/60
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may modify at least one texture memory object to support a data structure for one or more tensor objects. The apparatus may also determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object. Additionally, the apparatus may access data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction. The apparatus may also execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.
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公开(公告)号:US11074667B1
公开(公告)日:2021-07-27
申请号:US16821827
申请日:2020-03-17
Applicant: QUALCOMM Incorporated
Inventor: Aurangzeb , Litong Song , Ruihao Zhang
Abstract: Methods, systems, and devices for fast partial scalarization are described. A device may generate a representation of a set of vectors and a set of vector instructions associated with the set of vectors. The device may determine information associated with a vector in the set of vectors based on the representation, the information including an indication of splitting the vector and splitting one or more vector instructions associated with the vector. In some aspects, the device may associate the vector to one or more other vectors in the set of vectors based on one or more vector instructions related to the set of vectors. The device may update the information based on the associating and generate partially scalarized instructions based on the updating. The device may generate the partially scalarized instructions by excluding a subset of vector instructions and generating additional subsets of vector instructions and scalar instructions.
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