公开(公告)号：US20140177344A1

公开(公告)日：2014-06-26

申请号：US14025741

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Saravanan MARIMUTHU ,  Sachin BAPAT ,  Sakthivel PACKIRISAMY

IPC: G11C8/16 ,  G11C7/10

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/18 ,  G11C29/818 ,  G11C2207/108 ,  Y10T29/49117

Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Abstract translation: 公开了一种具有存储器件的集成电路元件; P型半导体区域，包括耦合到存储器件的第一存储器端口电路的第一半导体器件，并且被配置为当第一半导体器件被激活时能够访问存储器件; N型半导体区域，包括耦合到所述存储器件的第二存储器端口电路的第二半导体器件，并且被配置为当所述第二半导体器件被激活时能够访问所述存储器件; 以及分布在P型和N型半导体区域上的多条信号线，包括耦合以允许第一半导体器件被激活的第一存储器端口选择线; 耦合以允许第二半导体器件被激活的第二存储器端口选择线; 以及设置在第一存储器端口选择线和第二存储器端口选择线之间的时钟信号线。

公开(公告)号：US20160217227A1

公开(公告)日：2016-07-28

申请号：US14603281

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Peeyush Kumar PARKAR ,  Vijayalakshmi RANGANNA ,  Animesh DATTA ,  Sachin BAPAT

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: At least one critical path is determined of a plurality of paths in a network of logic elements. In addition, a plurality of original cells is determined in a critical path of the at least one critical path. Each intermediate output of the plurality of original cells is unconnected to any input external to the plurality of original cells. The plurality of original cells performs a particular logic function. Furthermore, the plurality of original cells are replaced with at least one replacement cell that performs the particular logic function. A number of cells of the at least one replacement cell is less than a number of cells of the plurality of original cells. The plurality of paths may be between a first memory stage and a second memory stage, and each of the at least one critical path may have a delay greater than a delay threshold.

Abstract translation: 确定逻辑元件网络中的多个路径的至少一个关键路径。 另外，在至少一个关键路径的关键路径中确定多个原始小区。 多个原始单元的每个中间输出与多个原始单元外部的任何输入未连接。 多个原始单元执行特定的逻辑功能。 此外，多个原始单元被替换为执行特定逻辑功能的至少一个替换单元。 所述至少一个替换单元的多个单元小于所述多个原始单元的多个单元。 多个路径可以在第一存储器级和第二存储器级之间，并且至少一个关键路径中的每一个可以具有大于延迟阈值的延迟。