公开(公告)号：US12298903B2

公开(公告)日：2025-05-13

申请号：US18314167

申请日：2023-05-09

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Saurabh Jaiswal ,  Vikrant Kumar ,  Swaraj Sha ,  Dharmesh Parikh

IPC: G06F12/06 ,  G11C11/406

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

公开(公告)号：US11749332B2

公开(公告)日：2023-09-05

申请号：US17174073

申请日：2021-02-11

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Saurabh Jaiswal ,  Vikrant Kumar ,  Swaraj Sha ,  Dharmesh Parikh

IPC: G11C29/00 ,  G11C11/406 ,  G06F12/06 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/40618 ,  G06F12/0607 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/40615 ,  G06F12/06

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.