公开(公告)号：US20150109045A1

公开(公告)日：2015-04-23

申请号：US14059361

申请日：2013-10-21

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Ohsang Kwon ,  Srivatsan Thiruvengadam

IPC: H03K19/0185

CPC classification number: H03K19/018585 ,  H03K19/018528

Abstract: A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits. The architecture can be used, for example, in CMOS system-on-a-chip integrated circuits implemented using metal-programmable standard cells. The architecture is also scalable for interfaces having different numbers of signals. The architecture can provide reduced area and improved performance.

Abstract translation: 提供了电压电平转换器的布局架构。 该架构包括电压电平移位器单元的特征和集成电路内的电压电平移位器单元的布置。 该架构可以用于例如使用金属可编程标准单元实现的CMOS片上集成电路。 该架构对于具有不同数量信号的接口也是可扩展的。 该架构可以提供面积缩小和性能提升。

公开(公告)号：US11824695B2

公开(公告)日：2023-11-21

申请号：US17579405

申请日：2022-01-19

Applicant: QUALCOMM Incorporated

Inventor： Darius Valaee ,  Patrick Isakanian ,  Srivatsan Thiruvengadam

IPC: H04L27/01 ,  H04L25/06 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/03343 ,  H04L25/069

Abstract: An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.