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公开(公告)号：US20160285453A1
公开(公告)日：2016-09-29
申请号：US14957188
申请日：2015-12-02
Applicant: QUALCOMM Incorporated
Inventor： Stephen Clifford Thilenius , Patrick Isakanian , Alvin Leng Sun Loke , Thomas Clark Bryan , LuVerne Ray Peterson
IPC: H03K19/0175 , H03K5/14
CPC classification number: H03K19/017518 , G11C7/1057 , H03K5/14 , H03K19/018507
Abstract: In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.
Abstract translation: 在一个实施例中，系统包括预驱动器电路和驱动器。 预驱动器电路由第一电源电压供电，并且被配置为输出预驱动信号。 驱动器包括具有耦合到第二电源电压的漏极的上拉NMOS晶体管和耦合到驱动器的输出的源，其中第二电源电压低于第一电源电压至少一个阈值电压 上拉式NMOS晶体管。 驱动器还包括耦合到上拉NMOS晶体管的栅极的驱动电路，其中驱动电路被配置为接收预驱动信号并且驱动上拉NMOS晶体管的栅极，其电压近似等于 根据预驱动信号的逻辑状态，第一电源电压将驱动器的输出驱动到高电平状态。
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公开(公告)号：US12021669B2
公开(公告)日：2024-06-25
申请号：US17985498
申请日：2022-11-11
Applicant: QUALCOMM Incorporated
Inventor： Patrick Isakanian , Darius Valaee
IPC: H04L25/03
CPC classification number: H04L25/03057
Abstract: An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.
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公开(公告)号：US12100474B2
公开(公告)日：2024-09-24
申请号：US17954852
申请日：2022-09-28
Applicant: QUALCOMM Incorporated
Inventor： Yong Xu , Satish Krishnamoorthy , Boris Dimitrov Andreev , Patrick Isakanian , Farrukh Aquil , Vikas Mahendiyan , Ravindra Arvind Khedkar
CPC classification number: G11C7/222 , G11C7/1066 , G11C7/14
Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.
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公开(公告)号：US09762231B2
公开(公告)日：2017-09-12
申请号：US14812516
申请日：2015-07-29
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Bo Yu , Stephen Clifford Thilenius , Reza Jalilizeinali , Patrick Isakanian
IPC: H03B1/00 , H03K3/00 , H03K17/082 , H03K19/003 , H03K19/0185
CPC classification number: H03K17/0822 , H03K19/00315 , H03K19/018521
Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.
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公开(公告)号：US11824695B2
公开(公告)日：2023-11-21
申请号：US17579405
申请日：2022-01-19
Applicant: QUALCOMM Incorporated
Inventor： Darius Valaee , Patrick Isakanian , Srivatsan Thiruvengadam
CPC classification number: H04L27/01 , H04L25/03343 , H04L25/069
Abstract: An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.
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Patent Agency Ranking
公开(公告)号：US09910482B2
公开(公告)日：2018-03-06
申请号：US14863890
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Michael Brunolli , Stephen Thilenius , Patrick Isakanian , Vaishnav Srinivas
CPC classification number: G06F1/3275 , G06F1/32 , G06F1/3209 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/4086 , G06F13/4243 , G11C7/1072 , G11C11/4074 , H04L25/0278 , Y02D10/14 , Y02D10/172 , Y02D50/20
Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.
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公开(公告)号：US11962440B2
公开(公告)日：2024-04-16
申请号：US17550993
申请日：2021-12-14
Applicant: QUALCOMM Incorporated
Inventor： Darius Valaee , Patrick Isakanian
CPC classification number: H04L25/03267 , G11C7/065 , H04L25/03057
Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.
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公开(公告)号：US11637553B2
公开(公告)日：2023-04-25
申请号：US17804383
申请日：2022-05-27
Applicant: QUALCOMM Incorporated
Inventor： Patrick Isakanian , Satish Krishnamoorthy
IPC: H03K17/687 , H03K19/0185 , H03K5/24 , G01R31/28
Abstract: An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.
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公开(公告)号：US11381238B1
公开(公告)日：2022-07-05
申请号：US17339195
申请日：2021-06-04
Applicant: QUALCOMM Incorporated
Inventor： Patrick Isakanian , Satish Krishnamoorthy
IPC: H03K17/687 , H03K19/0185 , H03K5/24 , G01R31/28
Abstract: An apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.
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公开(公告)号：US11018904B1
公开(公告)日：2021-05-25
申请号：US16729665
申请日：2019-12-30
Applicant: QUALCOMM Incorporated
Inventor： Prince Mathew , Ashwin Sethuram , Patrick Isakanian
Abstract: Certain aspects of the present disclosure provide methods and apparatus for equalizing a transmitter circuit for use in high-speed data links, such as in a serializer/deserializer (SerDes) scheme. One example transmitter circuit generally includes at least one driver stage, a first equalization circuit coupled to an output of the transmitter circuit, and a second equalization circuit coupled to an input of the at least one driver stage. One example method of transmitting data generally includes operating a transmit circuit comprising: at least one driver stage, a first equalization circuit coupled to an output of the transmitter circuit, and a second equalization circuit coupled to an input of the at least one driver stage; and selectively enabling at least one of the first equalization circuit or the second equalization circuit.
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