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公开(公告)号：US20190120905A1
公开(公告)日：2019-04-25
申请号：US15789663
申请日：2017-10-20
Applicant: QUALCOMM Incorporated
Inventor： David WONG , Neal HOROVITZ , Ta-Tung YEN , Sanghwa JUNG , Cheong KUN , Kin Siu FUNG
CPC classification number: H02J7/025 , G01R31/3648 , G01R31/382 , H02J7/04 , H02J50/10 , H02M3/158 , H03K5/24
Abstract: Enhanced reverse boosting detection in a wireless charging scheme is disclosed. In some implementations, a minimum mid-level input voltage regulation (VMID_MIN regulation) loop is provided to regulate an input voltage from a wirelessly coupled power source when a mid-level of the input voltage falls below a predetermined threshold. The input voltage is provided to a buck converter within a wireless charging receiver. An input missing poller signal generator is provided to generate an input missing poller (IMP) signal if the VMID_MIN regulation loop becomes active and the buck converter has entered a discontinuous mode.
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Patent Agency Ranking
公开(公告)号：US20210083572A1
公开(公告)日：2021-03-18
申请号：US17021591
申请日：2020-09-15
Applicant: QUALCOMM Incorporated
Inventor： Ta-Tung YEN , Guoyong GUO , Chunping SONG , Hector Ivan OPORTA
Abstract: Techniques and apparatus for controlling gate drivers of a switched-mode power supply (SMPS) circuit—such as a three-level buck converter, a divide-by-two charge pump, or an adaptive combination power supply circuit capable of switching therebetween—in a power-saving mode (e.g., a pulse-skipping mode). During such a power-saving mode in which a capacitor of a charge pump is disconnected from at least one power supply rail (e.g., first and second input nodes of the charge pump) and is coupled to power terminals of one or more drivers of the SMPS circuit, the capacitor is temporarily disconnected from the power terminals and temporarily coupled to the at least one power supply rail (e.g., for a few microseconds).
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公开(公告)号：US20230006555A1
公开(公告)日：2023-01-05
申请号：US17363948
申请日：2021-06-30
Applicant: QUALCOMM Incorporated
Inventor： Sanghwa JUNG , Chunping SONG , Ta-Tung YEN , Yue JING
Abstract: A three-level buck converter circuit configurable to transition between a three-level buck converter mode and a two-level buck converter mode and methods for regulating power using such a circuit. One example power supply circuit generally includes a three-level buck converter circuit and a control circuit coupled to the three-level buck converter circuit and configured to control operation of the three-level buck converter circuit between a three-level buck converter mode and a two-level buck converter mode. The three-level buck converter circuit generally includes a first switch, a second switch coupled to the first switch via a first node, a third switch coupled to the second switch via a second node, a fourth switch coupled to the third switch via a third node, a first capacitive element coupled between the first node and the third node, and an inductive element coupled between the second node and an output node.
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4.发明申请公开(公告)号：US20210083573A1
公开(公告)日：2021-03-18
申请号：US17021614
申请日：2020-09-15
Applicant: QUALCOMM Incorporated
Inventor： Ta-Tung YEN , Chunping SONG , Guoyong GUO , Hector Ivan OPORTA , Ahmed ABDELMOATY
Abstract: Techniques and apparatus for supplying power to gate drivers of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a SMPS circuit having a first input voltage node and a second input voltage node, and a charge pump. The charge pump generally includes a first capacitive element having a first terminal and a second terminal; a first switch coupled between a first input node of the charge pump and the first terminal of the first capacitive element; a second switch coupled between the second terminal of the first capacitive element and a second input node of the charge pump; a third switch coupled between the first terminal of the first capacitive element and the first input voltage node of the SMPS circuit; and a fourth switch coupled between the second terminal of the first capacitive element and the second input voltage node of the SMPS circuit.
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公开(公告)号：US20240055992A1
公开(公告)日：2024-02-15
申请号：US18489639
申请日：2023-10-18
Applicant: QUALCOMM Incorporated
Inventor： Sanghwa JUNG , Chunping SONG , Ta-Tung YEN , Yue JING
CPC classification number: H02M3/1582 , H02M3/07
Abstract: A three-level buck converter circuit configurable to transition between a three-level buck converter mode and a two-level buck converter mode and methods for regulating power using such a circuit. One example power supply circuit generally includes a three-level buck converter circuit and a control circuit coupled to the three-level buck converter circuit and configured to control operation of the three-level buck converter circuit between a three-level buck converter mode and a two-level buck converter mode. The three-level buck converter circuit generally includes a first switch, a second switch coupled to the first switch via a first node, a third switch coupled to the second switch via a second node, a fourth switch coupled to the third switch via a third node, a first capacitive element coupled between the first node and the third node, and an inductive element coupled between the second node and an output node.
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公开(公告)号：US20220311339A1
公开(公告)日：2022-09-29
申请号：US17216171
申请日：2021-03-29
Applicant: QUALCOMM Incorporated
Inventor： Ta-Tung YEN , Sanghwa JUNG , Xiaolin GAO
Abstract: Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.
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