BANDWIDTH REDUCTION FOR INSTRUCTION TRACING
    1.
    发明申请

    公开(公告)号:US20170249146A1

    公开(公告)日:2017-08-31

    申请号:US15057111

    申请日:2016-02-29

    CPC classification number: G06F11/3636 G06F11/36

    Abstract: Systems and methods pertain to reducing bandwidth of instruction tracing for a processor, using an Embedded Trace Macrocell (ETM). Packets, which include trace information for load/store instructions executed in the processor, are generated. A P-Header comprising commit information for load/store instructions of up to a maximum number of two or more packets is generated. The P-Header is generated for the maximum number of two or more packets if none of the load/store instructions in the maximum number of two or more packets were killed. If a load/store instruction in a packet was killed, a P-Header comprising commit information for the packet comprising the load/store instruction which was killed is generated and placed in an instruction trace immediately after that packet, even if the maximum number is not reached.

    REDUCTION OF DATA TRANSFER OVERHEAD

    公开(公告)号:US20250156187A1

    公开(公告)日:2025-05-15

    申请号:US18510088

    申请日:2023-11-15

    Abstract: Aspects of the disclosure are directed to reduction of data transfer overhead. In accordance with one aspect, increment a function call counter for an executed function call; decrement the function call counter for an executed return from function call; infer the indirect branch address based on a function call counter value and when a cumulative count of received executed atoms indicates a return from function call has been executed; oversaturate the function call counter at a maximum counter value if the function call counter contains the maximum counter value and a subsequent function call is executed; and undersaturate the function call counter at a minimum counter value if the function call counter contains the minimum counter value and a subsequent return from function call is executed.

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