公开(公告)号：US20250156396A1

公开(公告)日：2025-05-15

申请号：US18509115

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Richard SENIOR ,  Sundeep KUSHWAHA ,  Scott Russell BAUER ,  Gurvinder Singh CHHABRA ,  Norris GENG ,  Christopher KOOB ,  Sergei LARIN ,  Vipin SALI ,  Murali SOMANCHY ,  Aleksandr Sergeevich TARASIKOV

IPC: G06F16/23 ,  H03M7/30

Abstract: Aspects of the disclosure are directed to data integrity detection. In accordance with one aspect, an apparatus including a compressed data sector configured to store a compressed data; a meta data sector coupled to the compressed data sector, the meta data sector configured to indicate an invalid meta data index; and a compression/decompression engine coupled to the meta data sector, the compression/decompression engine configured to compress an original data to generate the compressed data and further configured to decompress the compressed data to generate a decompressed data.

公开(公告)号：US20160092492A1

公开(公告)日：2016-03-31

申请号：US14499148

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Michael ZIMMER ,  Richard SENIOR ,  Swaminathan SURESHCHANDRAN ,  Venkata Ramanan VENKATACHALAM JAYARAMAN

IPC: G06F17/30

CPC classification number: G06F16/2365 ,  G06F16/2246 ,  H03M7/3084 ,  H03M7/3088 ,  H03M7/40 ,  H03M7/6064 ,  H03M7/6076

Abstract: A string of data is partitioned into a set of blocks. Each block is compressed based on a set of initial dictionaries and a set of Huffman trees. Each block is associated by a pointer with an initial dictionary in the set of initial dictionaries and a Huffman tree in the set of Huffman trees used to compress that block. A compressed string of data includes the set of initial dictionaries, the set of Huffman trees, and the compressed blocks and associated pointers.

Abstract translation: 一串数据被分割成一组块。 每个块基于一组初始字典和一组霍夫曼树进行压缩。 每个块通过指针与初始字典集中的初始字典相关联，并且在用于压缩该块的霍夫曼树集合中的霍夫曼树相关联。 一个压缩的数据串包括一组初始字典，一组霍夫曼树，以及压缩的块和相关的指针。

公开(公告)号：US20250156187A1

公开(公告)日：2025-05-15

申请号：US18510088

申请日：2023-11-15

Applicant: QUALCOMM Incorporated

Inventor： Richard SENIOR ,  Venkatarami MORA ,  Suresh Kumar VENKUMAHANTI ,  Avinash GADDE ,  Christopher AHN ,  Sangchol LEE ,  Sanjana RAJEEV ,  Dhairya AGRAWAL

IPC: G06F9/38 ,  G06F9/30

Abstract: Aspects of the disclosure are directed to reduction of data transfer overhead. In accordance with one aspect, increment a function call counter for an executed function call; decrement the function call counter for an executed return from function call; infer the indirect branch address based on a function call counter value and when a cumulative count of received executed atoms indicates a return from function call has been executed; oversaturate the function call counter at a maximum counter value if the function call counter contains the maximum counter value and a subsequent function call is executed; and undersaturate the function call counter at a minimum counter value if the function call counter contains the minimum counter value and a subsequent return from function call is executed.

公开(公告)号：US20240403411A1

公开(公告)日：2024-12-05

申请号：US18697722

申请日：2022-11-17

Applicant: QUALCOMM Incorporated

Inventor： Sundeep KUSHWAHA ,  Arvind KRISHNASWAMY ,  Sergei LARIN ,  Can ACAR ,  Tianshuo SU ,  Awanish PANDEY ,  Richard SENIOR

IPC: G06F21/53 ,  G06F12/14 ,  G06F21/54

Abstract: Various embodiments include methods and devices for maintaining control flow integrity in computing devices. Embodiments may include identifying indirect function call candidate functions from a source code by a compiler, replacing, by the compiler, an indirect function call from the source code with a call to a wrapper function, and collocating the indirect function call candidate functions in at least one range of addresses of memory by a linker. The wrapper function may be configured to determine whether an address to be passed to the indirect function call is within the at least one range of addresses of memory.

公开(公告)号：US20190073223A1

公开(公告)日：2019-03-07

申请号：US15695733

申请日：2017-09-05

Applicant: QUALCOMM Incorporated

Inventor： Richard SENIOR ,  Raghuveer RAGHAVENDRA ,  Gurkanwal BRAR ,  Arvind GOVINDARAJ

IPC: G06F9/38 ,  G06F12/0855

Abstract: Systems and methods for branch prediction include detecting a subset of branch instructions which are not fixed direction branch instructions, and for this subset of branch instructions, utilizing complex branch prediction mechanisms such as a neural branch predictor. Detecting the subset of branch instructions includes using a state machine to determine the branch instructions whose outcomes change between a taken direction and a not-taken direction in separate instances of their execution. For the remaining branch instructions which are fixed direction branch instructions, the complex branch prediction techniques are avoided.

公开(公告)号：US20170371797A1

公开(公告)日：2017-12-28

申请号：US15192984

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC: G06F12/0877 ,  G06F12/0842

CPC classification number: G06F12/0877 ,  G06F12/023 ,  G06F12/0842 ,  G06F12/0855 ,  G06F12/0886 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/604 ,  H03M7/30

Abstract: Some aspects of the disclosure relate to a pre-fetch mechanism for a cache line compression system that increases RAM capacity and optimizes overflow area reads. For example, a pre-fetch mechanism may allow the memory controller to pipeline the reads from an area with fixed size slots (main compressed area) and the reads from an overflow area. The overflow area is arranged so that a cache line most likely containing the overflow data for a particular line may be calculated by a decompression engine. In this manner, the cache line decompression engine may fetch, in advance, the overflow area before finding the actual location of the overflow data.

公开(公告)号：US20170371792A1

公开(公告)日：2017-12-28

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro OPORTUS VALENZUELA ,  Nieyan GENG ,  Christopher Edward KOOB ,  Gurvinder Singh CHHABRA ,  Richard SENIOR ,  Anand JANAKIRAMAN

IPC: G06F12/0871 ,  G06F12/0868

CPC classification number: G06F12/0871 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/281 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/401 ,  G06F2212/601 ,  G06F2212/608

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time

公开(公告)号：US20250165143A1

公开(公告)日：2025-05-22

申请号：US18513393

申请日：2023-11-17

Applicant: QUALCOMM Incorporated

Inventor： Kan WANG ,  Norris GENG ,  Richard SENIOR ,  Christopher KOOB ,  Pranav VERMA ,  Suresh Kumar VENKUMAHANTI ,  Gurvinder Singh CHHABRA

IPC: G06F3/06

Abstract: A method for reducing a memory footprint of data stored in a compressed memory subsystem is described. The method includes selecting a read/write data to store in the compressed memory subsystem. The method also includes searching a first compressed data storage pool of the compressed memory subsystem corresponding to a compressed size of the read/write data to identify a first free data block. The method further includes storing the read/write data in a second free data block from a second compressed data storage pool of the compressed memory subsystem corresponding to a compressed size of the read/write data if the first compressed data storage pool is exhausted.

公开(公告)号：US20230236979A1

公开(公告)日：2023-07-27

申请号：US17572472

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris GENG ,  Richard SENIOR ,  Gurvinder Singh CHHABRA ,  Kan WANG

IPC: G06F12/084 ,  G06F12/0811 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0811

Abstract: A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.

公开(公告)号：US20230236961A1

公开(公告)日：2023-07-27

申请号：US17572471

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris GENG ,  Richard SENIOR ,  Gurvinder Singh CHHABRA ,  Kan WANG

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/401

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.